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 MC74HC03A Quad 2-Input NAND Gate with Open-Drain Outputs
High-Performance Silicon-Gate CMOS
The MC74HC03A is identical in pinout to the LS03. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC03A NAND gate has, as its outputs, a high-performance MOS N-Channel transistor. This NAND gate can, therefore, with a suitable pullup resistor, be used in wired-AND applications. Having the output characteristic curves given in this data sheet, this device can be used as an LED driver or in any other application that only requires a sinking current. * Output Drive Capability: 10 LSTTL Loads With Suitable Pullup Resistor * Outputs Directly Interface to CMOS, NMOS and TTL * High Noise Immunity Characteristic of CMOS Devices * Operating Voltage Range: 2 to 6V * Low Input Current: 1A * In Compliance With the JEDEC Standard No. 7A Requirements * Chip Complexity: 28 FETs or 7 Equivalent Gates
DESIGN GUIDE
Criteria Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product * Equivalent to a two-input NAND gate Value 7.0 1.5 5.0 0.0075 Unit ea ns W pJ
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14 PDIP-14 N SUFFIX CASE 646 MC74HC03AN AWLYYWW 1 14 SOIC-14 D SUFFIX CASE 751A 1 14 TSSOP-14 DT SUFFIX CASE 948G HC 03A ALYW HC03A AWLYWW
1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week
FUNCTION TABLE
Inputs Output B L H L H Y Z Z Z L
LOGIC DIAGRAM
OUTPUT PROTECTION DIODE
VCC
A L L H H
PIN 14 = VCC PIN 7 = GND * Denotes open-drain outputs
3,6,8,11
Y*
Z = High Impedance A B 1,4,9,12 2,5,10,13
Pinout: 14-Lead Packages (Top View)
VCC 14 B4 13 A4 12 Y4 11 B3 10 A3 9 Y3 8
ORDERING INFORMATION
Device MC74HC03AN MC74HC03AD MC74HC03ADR2 MC74HC03ADT Package PDIP-14 SOIC-14 SOIC-14 TSSOP-14 TSSOP-14 Shipping 2000 / Box 55 / Rail 2500 / Reel 96 / Rail 2500 / Reel
1 A1
2 B1
3 Y1
4 A2
5 B2
6 Y2
7 GND
MC74HC03ADTR2
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 8
Publication Order Number: MC74HC03A/D
MC74HC03A
IIIIIIIIIIIIIIIIIIII II I IIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIII II I II I I III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature - 65 to + 150 260
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
_C _C
Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
IIII I I I II IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I IIII I II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I
Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC - 55 0 0 0 + 125 1000 500 400
RECOMMENDED OPERATING CONDITIONS
_C
ns
tr, tf
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol VIH Parameter Minimum High-Level Input Voltage
Condition Vout = 0.1V or VCC -0.1V |Iout| 20A
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 6.0 6.0 6.0
Guaranteed Limit -55 to 25C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 0.1 0.1 0.1 0.26 0.26 0.26 0.1 1.0 0.5 85C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 0.1 0.1 0.1 0.33 0.33 0.33 1.0 10 5.0 125C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 0.1 0.1 0.1 0.40 0.40 0.40 1.0 40 10 A A A Unit V
VIL
Maximum Low-Level Input Voltage
Vout = 0.1V or VCC - 0.1V |Iout| 20A
V
VOL
Maximum Low-Level Output Voltage
Vout = 0.1V or VCC - 0.1V |Iout| 20A Vin = VIH or VIL |Iout| 2.4mA |Iout| 4.0mA |Iout| 5.2mA
V
Iin ICC IOZ
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Maximum Three-State Leakage Current
Vin = VCC or GND Vin = VCC or GND Iout = 0A Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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MC74HC03A
AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)
Symbol tPLZ, tPZL Parameter Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 Guaranteed Limit -55 to 25C 120 45 24 20 75 27 15 13 10 10 85C 150 60 30 26 95 32 19 16 10 10 125C 180 75 36 31 110 36 22 19 10 10 Unit ns
tTLH, tTHL
Maximum Output Transition Time, Any Output (Figures 1 and 2)
ns
Cin Cout
Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State)
pF pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Per Buffer)* 8.0 pF * Used to determine the no-load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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MC74HC03A
VCC tr INPUT A 90% 50% 10% tPZL OUTPUT Y 90% 50% 10% tTHL tPLZ tf VCC GND HIGH IMPEDANCE 10% VOL *Includes all probe and jig capacitance DEVICE UNDER TEST
1k OUTPUT
Rpd TEST POINT CL*
Figure 1. Switching Waveforms
25 TYPICAL T=25C 20 I D, SINK CURRENT (mA) T=25C 15 T=85C 10 T=125C EXPECTED MINIMUM* 5 VCC=5V
Figure 2. Test Circuit
0 0 1 2 3 4 VO, OUTPUT VOLTAGE (VOLTS) 5
*The expected minimum curves are not guarantees, but are design aids.
Figure 3. Open-Drain Output Characteristics
VCC PULLUP RESISTOR A1 B1 A2 B2
1/4 HC03 1/4 HC03
Y1
VCC + VR - + VF - LED1
1/4 HC03 1/4 HC03
VCC
OUTPUT
Y2 LED2 LED ENABLE
DESIGN EXAMPLE CONDITIONS: ID USING FIGURE NO TAG TYPICAL CURVE, at ID=10mA, VDS
An Bn
1/4 HC03
Yn
^10mA ^0.4V NR + VCC * VF * VO + 5V * 1.7V * 0.4V 10mA + 290W
ID
OUTPUT = Y1 * Y2 * . . . * Yn = A1B1 * A2B2 * . . . * AnBn
USE R = 270
Figure 4. Wired AND
Figure 5. LED Driver With Blanking
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MC74HC03A
PACKAGE DIMENSIONS
PDIP-14 N SUFFIX CASE 646-06 ISSUE L
14 8
B
1 7
NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01
A F C N H G D
SEATING PLANE
L
J K M
SOIC-14 D SUFFIX CASE 751A-03 ISSUE F
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
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MC74HC03A
PACKAGE DIMENSIONS
TSSOP-14 DT SUFFIX CASE 948G-01 ISSUE O
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
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6
EE CC EE CC
A -V-
MC74HC03A
Notes
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MC74HC03A
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MC74HC03A/D


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